. WIOSCA 2008 Advanced Program



WIOSCA-08 Program




 Session 1: CMP Resource Management and Synchronization


 Memory Management on Chip-MultiProcessors with on-chip Memories     Paper - Slides
  • Carlos Villavieja, Universitat Politècnica de Catalunya
  • Isaac Gelado, Universitat Politècnica de Catalunya
  • Alex Ramirez, Universitat Politècnica de Catalunya
  • Nacho Navarro, Universitat Politècnica de Catalunya

 Understanding the overhead of the spin-lock loop in CMT architectures     Paper - Slides
  • Vladimir Cakarevic, Barcelona Supercomputing Center
  • Petar Radojkovic, Barcelona Supercomputing Center
  • Francisco Cazorla, Barcelona Supercomputing Center
  • Roberto Gioiosa, Barcelona Supercomputing Center
  • Alex Pajuelo, Barcelona Supercomputing Center
  • Javier Verdu, Barcelona Supercomputing Center
  • Mario Nemirovsky, Barcelona Supercomputing Center
  • Mateo Valero, Universitat Politècnica de Catalunya

 Session 2: Interaction with Emerging Architectures


 Operating System Support for Shared-ISA Asymmetric Multi-core Architectures     Paper - Slides
  • Tong Li, Intel
  • Paul Brett, Intel
  • Barbara Hohlt, Intel
  • Rob Knauerhase, Intel
  • Sean D. McElderry, Intel
  • Scott Hahn, Intel

 GreenRT: A Framework for the Design of Power-Aware Soft Real-Time Applications     Paper - Slides
  • Bo Chen, Simon Fraser University
  • William Pak Tun Ma, Simon Fraser University
  • Yan Tan, Simon Fraser University
  • Alexandra Fedorova, Simon Fraser University
  • Greg Mori, Simon Fraser University

 OS Paradigms Adaption to Fit New Architectures     Paper - Slides
  • Xavi Joglar, Universitat Politècnica de Catalunya
  • Judit Planas, Universitat Politècnica de Catalunya
  • Marisa Gil, Universitat Politècnica de Catalunya

  Session 3: OS Scheduling for Multi-core Design (1)


 Asymmetricity Aware Scheduling Algorithms for Asymmetric Processors     Paper - Slides
  • Nagesh Lakshiminarayana, Georgia Institute of Technology
  • Sushma Rao, Georgia Institute of Technology
  • Hyesoon Kim, Georgia Institute of Technology

 Analyzing the Effectiveness of Multicore Scheduling Using Performance Counters     Paper - Slides
  • Stephen Ziemba, Perdue University
  • Gautam Upadhyaya, Perdue University
  • Vijay Pai, Perdue University

  Session 4: OS Scheduling for Multi-core Design (2)


 Scheduling on Heterogeneous Multicore Processors Using Architectural Signatures     Paper - Slides
  • Daniel Shelepov, Simon Fraser University
  • Alexandra Fedorova, Simon Fraser University

 Evaluation of Cell BE SPU Scheduling for Multi-programmed Systems     Paper - Slides
  • Julio M. Merino-Vidal, Universitat Politècnica de Catalunya
  • Isaac Gelado, Universitat Politècnica de Catalunya
  • Nacho Navarro, Universitat Politècnica de Catalunya